Recent advances in the field of metal-oxide-semiconductor ("MOS") technology have included scaling down of gate dielectric thickness. As the thickness of these devices decreases, a number of problems have been encountered. For example, as the overall size becomes "ultra-thin", e.g., less than 75 .ANG., the quality of the Si/SiO.sub.2 interface characteristics play dominate roles in determining the quality of gate oxide. In fact, film thicknesses below 25 .ANG. suffer from excessive tunneling current (&gt;1A/cm.sup.2) problems as they approach the tunneling limit. On such thin gate dielectrics, suppression of boron diffusion from p.sup.+ poly gate into channel regions is also a serious concern. These problems have severely hampered the ability to fabricate integrated circuit utilizing "ultra-thin" designs.
To address such problems, the art has sought to provide a reliable, high quality gate dielectric having the desired properties of low defect density, D.sub.o, and high breakdown field strength, F.sub.bd, that retains its quality during advanced processing. Although the art has been able to provide oxide/nitride (ON) and oxide/nitride/oxide (ONO) structures having excellent (lower D.sub.o) behavior, such structures have suffered from serious charge trapping problems. That is, because the oxidizing species will not penetrate the nitride layer, the interface (nitride/oxide) traps cannot be annealed. Thus, nitride structures cannot be effectively employed on gate dielectrics.
Stacked oxides, however, have alleviated such problems, thereby achieving simultaneous solutions to low leakage (low D.sub.o) and low trap densities (D.sub.it,Q.sub.f).
For example, U.S. Pat. No. 4,851,370 includes a composite stack synthesized by a three-step grow-deposit-grow technique where the growing steps are conducted at pressures equal to or greater than one atm to achieve ultra-low D.sub.o, D.sub.it oxides with a planar and stress free Si/SiO.sub.2. This patent is incorporated by reference in its entirety for all purposes.
Alternatively, a copending U.S. application of the same assignee, i.e., U.S. Application Serial No. (Brady Apr. 10, 1935) which is incorporated herein by reference, discloses certain low pressure techniques for providing a stacked oxide arrangement for thinner gate dielectrics, e.g., less than 65 .ANG.. This method can also involve a sequence of grow-deposit-grow steps, however, in this case, the steps are performed in a zone of low pressure, e.g., a pressure that is preferably about 200 milliTorr to 950 milliTorr. The use of such low pressures can, e.g., retard the oxidation rate at which the first and second oxide layers are grown.
The resulting stack structure has superior electrical and substructural properties as compared to that provided by a conventional oxidation scheme. The method disclosed in this copending application also allows the ultra-thin oxide layers to be formed in a single furnace cluster step that can significantly decrease the cost of the process.
Despite the significant advantages that can be associated with these stacked oxide arrangements, they have not effectively resolved boron (B) diffusion issues.
Thus, the need still exists for a gate dielectric which is capable of providing both the advantages associated with the stacked oxides, e.g., a low interfacial trap, and which is also a suitable boron blocker.